As a result of innovations in integrated circuit and packaging fabrication processes, dramatic performance improvements and cost reductions have been obtained in the electronics industry. The speed and performance of chips, and hence the computer systems that utilize them, are ultimately dictated by the minimum printable feature sizes obtainable through lithography. The lithographic process, which replicates patterns rapidly from one wafer or substrate to another, also determines the throughput and the cost of electronic systems. A typical lithographic system includes exposure tools, masks, resist, and all of the processing steps required to transfer a pattern from a mask to a resist, and then to devices.
Chromeless phase lithography (CPL) is a particular lithographic technique that utilizes chromeless mask features to define circuit features with pairs of 0-degree and 180-degree phase steps. These phase steps can be obtained, for example, by etching a trench in a quartz substrate to a depth corresponding to a 180-degree phase shift at the illumination wavelength of the lithography system. Alternatively, phase shift layers can be formed as mesas on a quartz substrate.
CPL mask designs can be created by assigning circuit features to different zones or groups, based on the physical attributes of those features. One example of such a system, which is known to the art, is depicted in FIGS. 1-2. The system illustrated therein utilizes three such zones. The boundaries of each zone are defined herein for illustrative purposes only. In the system of FIGS. 1-2, circuit features having widths of 90 nm or less are assigned to Zone 1. These features are constructed with 100% transmission phase-shifted structures and are printed utilizing adjacent phase edges. Hence, these features are chromeless features. Features having a width greater than 130 nm are deemed to reside in Zone 3, and are printed utilizing chrome features. Features having widths between 90 nm and 130 nm are deemed to reside in Zone 2. The features of Zone 2 are too wide to be defined using the 100% transmission of pure CPL and may be too narrow to be printed solely in chrome, and hence are printed using a so-called ‘zebra’ pattern treatment. The zebra pattern treatment employs a plurality of sub-resolution chrome patches which are formed on the chromeless feature pattern to be imaged and which are intended to reduce the average optical transmission of the otherwise chromeless feature. If correctly defined on the mask, the zebra pattern treatment can result in improved lithographic margins for features that reside in Zone 2 compared to either chromeless or chrome features.
While CPL processes of the type depicted in FIGS. 1-2 have some desirable attributes, the zebra pattern utilized in these processes contains structures that are sub-resolution. Moreover, the zebra structures are secondary features formed in a second writing step which typically involves use of an optical pattern generator (the first writing step being an electron beam pattern generator used to form the primary, chromeless features). Hence, the sub-resolution features in the zebra structure may not be formed using a high resolution pattern generator and must also be registered with the primary, chromeless features. Consequently, the mask utilized to take advantage of these structures is difficult to fabricate, inspect and repair. The zebra structures also significantly increase the size of the pre- and post-fracture database, hence making fabrication of the mask a computationally intensive undertaking. Moreover, in practice, critical dimension (CD) uniformity and control on zebra structures has proven to be less than desirable.
There is thus a need in the art for a CPL mask design that overcomes the aforementioned infirmities. In particular, there is a need in the art for a method for simplifying the fabrication of CPL masks, particularly for Zone 2 features. These and other needs are met by the devices and methodologies described herein.